Cyclic Redundancy Check Simulation

written by Crystal Barchet and Teresa Carrigan

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THINGS TO NOTICE

When the orignal message is all zeroes, the CRC remainder added is also all zeroes.

The CRC remainder will always be on fewer bit than the generator.

When you bring down the generator, it moves over until its leftmost 1 is under the leftmost one on the line above. Enough bits on the right are brought down so that the line above extends to the same column as the rightmost 1 of the generator.

All generators begin and end with a 1. That is because leading zeroes are stripped, and the mathematical theory behind how CRC works insists that generators be odd, and prefers them to be prime. With a prime generator, a generator of length n can detect all burst errors of length (n - 1) and will detect many errors of longer lengths. If an even generator is used, then we can not be certain to detect all burst errors of length (n - 1).

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THINGS TO TRY

Set the slow-motion slider to about .2 seconds (or slower) and press the step button several times. Watch the demonstration of each step.

Set the slow-motion slider to about .2 seconds and press the go button. Watch the entire demonstration.

Do each step by hand, then press step to check your work.

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Applets on this website were written by Teresa Carrigan in 2004, for use in computer science courses at Blackburn College, with the exception of the Fireworks applet. The applets made with NetLogo require Java 1.4.1 or higher to run. The applets made with NetBeans require Java 1.4.2 or higher to run. Applets might not run on Windows 95 or Mac OS 8 or 9. You may obtain the latest Java plugin from Sun's Java site.